The present invention relates, in general, to the fabrication technology of MOS type semiconductor devices, and, more in particular, to that relative to power VDMOS devices or devices of modulated conductivity either in discrete form or in integrated form, where the symbol VDMOS identifies a MOS structure with horizontal diffused channel and vertical path of the current.
After a protracted evaluation of different structures, the VDMOS structure appears to have been adopted by the manufacturers of semiconductor devices as the structure which, at present, realizes the best compromise in the quest of an ideal power switching device.
In this respect, making the smallest possible the "ON-resistance" parameter, i.e. the ohmic resistance offered by the device under conduction conditions, represents a problem of prime importance in designing such power or conductivity modulation MOS devices.
The ON resistance of a VDMOS device is primarily determined by the value of two resistive contributions: the MOS channel resistance and the resistance of the epitaxial layer.
Many sudies of recent and less recent publication, among which: the article "The Optimization of ON-Resistance in Vertical DMOS Power Devices with Linear and Hexagonal Surface Geometries" by Kenneth Board, David J. Byrne and Malcom S. Towers appeared on IEEE Transactions on Electron Devices, Vol. ED. 31 No. 1, January 1984; and "Les limites de la resistance a l'eetat passant des DMOS de puissance" by Pierre Aloisi of Motorola of Toulouse - France, have evidenced that the main and determinant one of said contributions to the value of the ON resistance of said devices is tied essentially to the ratio between the extension of the outer boundary of the MOS channel and the area of the DMOS cell. Therefore, in order to decrease the ON resistance, it is necessary to make as large as possible said ratio by increasing the density of integration. In other words, being said power MOS devices formed by a large number of elementary cells connected in parallel, it is necessary to reduce as far as possible the dimensions of single cells and to increase their number.
In practice, the limitation to the reduction of the value of the ON resistance of VDMOS cells power devices, is determined by technological limits of area definition. Obviously, for fabricating such devices, the most sofisticated techniques are utilized, that is the VLSI processes (i.e. Very Large Scale Integration) while the shape of the individual VDMOS cells may be rectangular, square or hexagonal.
In the structure of a typical DMOS cell, e.g. n channel, whose channel is obtained by exploiting the difference of lateral diffusion of a "p" dopant and of a "n" dopant under the gate polycrystalline silicon, there exists a more heavily doped p.sup.+ central region for short circuiting the p body with the n.sup.+ source (such central region being known with the name of p.sup.+ short).
This region should be as large as possible in the horizontal direction, though it should not encroach into the p region, that is alter the doping level of the p silicon region channel and consequently increase the value of the threshold voltage of the DMOS cell.
On the other hand, such a p.sup.+ short region should extend as far as possible in a horizontal sense in order to lower the gain of the parasitic n.sup.+ /p/n.sup.- transistor which could, under certain circuit situations, interfere and jeopardize the characteristics of the power MOS device or of the equivalent conductivity modulation MOS device.
These stringent geometrical requisites of the p.sup.+ short region reflect in the necessity to proceed to a stage of accurate alignment of the "window" or aperture, for the implantation and diffusion of the dopant to form said p.sup.+ silicon region, in relation to the edge of the layer of the gate polycrystalline silicon. In practice, the fabrication process contemplates a first masking for implating boron followed by the formation of the layer of thermally produced gate oxide, by the deposition of polycrystalline silicon, by the definition of the gate polycrystalline silicon, thence followed by a second boron implantation to form silicon regions in the channel regions.
The multiplication of critical stages of accurate area definition hardly conciliate itself with the previously discussed requirement of increasing as far as possible the degree of integration with the aim of decreasing the ON resistance of the device.